High pin count devices, typically in excess of 1900 pins at 1 mm pitch, are driving printed circuit boards (PCBS) to have upwards of 28 layers, which dramatically increases the cost of the card as well as increasing reliability problems, e.g. because such thick cards push through-hole board (THB) via technology to its limits resulting in manufacturing defects and failures caused by thermal expansion of the cards. In fact, for a typical circuit board, a 25% increase in the number of layers from 20 to 25 results in a 100% cost increase for example.
Furthermore, although the cost of a circuit board is typically only about 14% of the printed board assembly (PBA) cost, the cost of a failed PCB is 100% of the PBA cost. This is because the entire PBA is usually scrapped when the PCB fails. Therefore, reducing the number of PCB failures saves more than just the cost of the PCB, which in the case of a 28 layer board is already a very significant cost savings.
In addition, since PCB design is typically at the tail end of the PBA design process extra layers are often added to the PCB design to accommodate deficiencies in earlier stages of the PBA design. This practice further adds to the layer count, hence the cost, of a PCB. In fact, it is often a single component, usually a high pin count application specific integrated circuit (ASIC), that determines the maximum layer count of a PCB.
In view of the foregoing, there is a need to provide a method of designing PCBs with lower layer counts, thereby reducing the manufacturing cost of PCBs while improving their reliability, which will also lead to cost savings with respect to PBA failures.